L6451 28 channel ink jet driver 40v dmos output breakdown precise output energy esd output protection with clamp- ing diodes very low quiescent current package: plcc44 description the L6451 is realized in multipower bcd tech- nology which combines isolated dmos power transistors with cmos and bipolar circuits on the same ic. by using mixed technology it has been possible to optimize the logic circuitry and the power stage to achieve the best possible perform- ances. intended to be used in ink jet printer applications as 4 to 28 (2 x 14) lines selectable decoder/driver, the L6451 device driver has the advantages of low power cmos inputs and logic, with 28 high current and high voltage dmos outputs capable of sustaining a maximum of 40v. on system power up the output drivers are locked out using the chip enable function; two enable in- puts are available for the different driver banks. an internal power-on system is implemented in order to avoid wrong output commutation during the supply voltage transients. using a mask option during manufacturing allows a different decoding. control of the energy delivered to the print head is made by means of a special circuitry. all driver outputs are capable of withstanding a contact discharge of 8kv with the ic biased. december 2000 ? block diagram (case of 4 bit) plcc44 multipower bcd technology 1/8
plcc44 pin connection (top view) L6451 2/8
pin functions name function v dd 5v logic supply. gnd logic and power ground. out0 to out27 dmos outputs. clamp this pin has to be connected to the power supply voltage of the head resistors. each of the output dmos have their drain connected with the anode of a protection diode, all the cathodes of the protection diodes are connected to the clamp pin. in order to have the device supplied, the clamp pin needs to be connected to the power.. ina, inb, inc, ind decoder inputs. com1, com2 a low logic input on these pins enables the outputs selected by the decoder inputs. chip enable a logic high enable the chip. thermal data symbol parameter value unit r th j-amb thermal resistance junction-ambient max. 65 (*) c/w (*) device mounted on pcb. absolute maximum ratings symbol parameter value unit v out output voltage 40 v v clamp output clamping voltage 40 v i out output continuous current 0.8 a i peak output peak current (with duty cycle = 10% t on = 4 m s) 2 a t j junction temperature 150 c v dd logic supply voltage 7 v v in input voltage range -0.3v to v s +0.3 v t amb operating temperature range 0 to 70 c t stg storage temperature range -55 to 150 c L6451 3/8
d.c. electrical characteristics at t amb = 25 c, v dd = 5v, v clamp = 18v (unless otherwise specified). symbol parameter test condition min. typ. max. unit v dd logic supply voltage 4.75 5 5.25 v v clamp clamping voltage 9 38 v v il low level input voltage 1.2 v v ih high level input current v dd -1.2 v i ll low level input current v in = v il -200 m a i lh high level input current v in = v ih 10 m a i dd logic supply current (independent from the output conditions) 5ma v out output saturation voltage tj 25 c d.c. 0.4a tj 25 c d.c. 0.5a tj 90 c d.c. 0.4a tj 90 c d.c. 0.5a 0.9 1.1 1.4 1.7 v v v v d v ce output saturation absolute voltage variation around the typ. values for extended temperature ranges tj = 25 c to 90 c d.c.: 0.4a tj = 25 c to 90 c d.c.: 0.5a 0.2 0.25 v v r ds on 2.2 w a.c. electrical characteristics at t amb = 25 c, v dd = 5v. symbol signal name parameter test condition min. typ. max. unit t s ina, inb, inc, ind vs comn set - up time 30 ns t h ina, inb, inc, ind vs comn hold time 0 ns t on com1,2,3,4 v s out 0 to n turn - on time i out = 0.5a, r l = 39 w t j = 25 to 90 c 150 ns t off com1,2,3,4 v s out 0 to n turn - off time i out = 0.5a, r l = 39 w t j = 25 to 90 c 150 ns t r rise time 100 ns t f fall time 100 ns t wout output pulse width t win = 3.5 m s r l = 40 w i out = 0.5a - 20 t win + 80 ns d p d maximum allowable variation of the output power transmitted by each driver to the resistive load r l = 39 w v clamp = 18v 4% d p d maximum allowable variation of the output power transmitted by each driver to the resistive load r l = 40 w v clamp = 18v ?4 % L6451 4/8
figure 1: timing waveforms output selection decoder truth table ind inc inb ina (lsb) outputs 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.27 1.26 2.25 3.24 4.23 5.22 6.21 7.20 8.19 9.18 10.17 11.16 12.15 13.14 all off all off L6451 5/8
figure 2: application circuit L6451 6/8
plcc44 dim. mm inch min. typ. max. min. typ. max. a 17.4 17.65 0.685 0.695 b 16.51 16.65 0.650 0.656 c 3.65 3.7 0.144 0.146 d 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 0.68 0.027 e 14.99 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 f 0.46 0.018 f1 0.71 0.028 g 0.101 0.004 m 1.16 0.046 m1 1.14 0.045 outline and mechanical data L6451 7/8
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com L6451 8/8
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